The present invention relates to copper (Cu) and/or Cu alloy metallization in semiconductor devices. The present invention is applicable to manufacturing high-speed integrated circuits having submicron design features and high conductivity interconnect structures.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnect pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as device geometric shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing an interdielectric layer on a conductive layer comprising at least one conductive pattern, forming an opening through the interdielectric layer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interlayer dielectric is typically removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Cu and Cu alloys have received considerable attention as candidates for replacing Al in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-à-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring. However, due to Cu diffusion through interdielectric layer materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), Tungsten (W), tungsten nitride (WN), Ti-TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the interlayer dielectric, but includes interfaces with other metals as well.
There are additional problems attendant upon conventional Cu interconnect methodology employing a diffusion barrier layer (capping layer). For example, conventional practices comprise forming a damascene opening in an interdielectric layer, depositing a barrier layer such as TaN, lining the opening and on the surface of the interdielectric layer, filling the opening with Cu or a Cu alloy layer, CMP, and forming a capping layer on the exposed surface of the Cu or Cu alloy. It was found, however, that capping layers, such as silicon nitride, deposited by plasma enhanced chemical vapor deposition (PECVD), exhibit poor adhesion to the Cu or Cu alloy surface. Consequently, the capping layer is vulnerable to detamination, as by peeling due to scratching, stresses or poor adhesion resulting from subsequent deposition of layers. As a result, the Cu or Cu alloy is not entirely encapsulated and Cu diffusion occurs, thereby adversely affecting device performance and decreasing the electromigration resistance of the Cu or Cu alloy interconnect member. Moreover, conventional PECVD silicon nitride capping layers have a density of about 2.62 g/cm3 and, hence, are not particularly effective as an etch stop layer furring formation of interconnects for subsequent metallization levels.
In application Ser. No. 09/131,872 filed on Aug. 10, 1998 now U.S. Pat. No. 6,165,894 issued Dec. 26, 2000 the adhesion problem of a silicon nitride capping layer to a Cu interconnect was addressed by treating the exposed surface with an ammonia-containing plasma and depositing a silicon nitride capping layer thereon. In application Ser. No. 09/208,245 filed on Dec. 9, 1998 now U.S. Pat. No. 6,253,523 issued Nov. 28, 2000, the adhesion problem of a silicon nitride capping layer to a Cu interconnect was addressed by initially treating the exposed surface with an ammonia-containing plasma and then depositing a silicon nitride capping layer thereon under high density plasma conditions.
As design rules extend deeper into the submicron range, such as about 0.18 micron and under,. e.g., about 0.15 micron and under, the reliability of the interconnect pattern becomes increasingly critical. Therefore, the adhesion of capping layers to Cu interconnects and the accuracy of interconnects for vertical metallization levels require even greater reliability. Accordingly, there exists a need for methodology enabling the formation of encapsulated Cu and Cu alloy interconnect members for vertical metallization levels with greater accuracy and reliability.
An advantage of the present invention is a method of manufacturing a semiconductor device having highly reliable Cu or Cu alloy interconnect members.
Another advantage of the present invention is an efficient, cost-effective method of manufacturing a semiconductor device comprising a Cu or Cu alloy interconnect member having a dense silicon nitride capping layer tightly adhered thereto.
Additional advantages and other features of the present invention will be set forth in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: treating a surface of a copper (Cu) or Cu alloy layer with a plasma containing nitrogen and ammonia in a reaction chamber to reduce copper oxide on the surface; and in-situ forming a barrier layer on the treated surface of the Cu or Cu alloy layer under high density plasma conditions in the presence of nitrogen in the same reaction chamber.
Embodiments of the present invention comprise treating the surface of the Cu or Cu alloy layer within a plasma containing ammonia and nitrogen for up to about 30 seconds, e.g., about 1 to about 5 seconds, to reduce the copper oxide on the surface, and then introducing silane into the same reaction chamber to deposit a silicon nitride barrier layer on the treated surface in the presence of nitrogen. Embodiments of the present invention further include depositing a silicon nitride barrier layer under high density plasma conditions in the presence of ammonia, nitrogen and silane for about 1 to about 5 seconds to form a silicon nitride barrier layer at a thickness of about 150 xc3x85 to about 1,000 xc3x85.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.